School of Computer Science

Current Members

• Group coordinator Prof. Alex Shafarenko (Professor of Software Engineering) e-mail
• Prof. Bruce Christianson (Professor of Informatics)
• Colin Egan
• Patrick Quick
• Steve Hunt
• Sven Bodo Scholz
• Gordon Steven (Visiting Research Fellow)
• Prof. Lucian Vintan (Visiting Research Fellow)

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Current PhD Students

• James Hansen
• Jason McGuiness
• Michael Hicks

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Compiler Technology Research

Our work is focused on distributed array processing in conjunction with Computational Grids. We have a track record in languages for parallel computing which goes back to the early 90s when we proposed several data-parallel languages, most notably F-code which was used as a virtual machine in various compiler projects. More recently we have been developing the concept of distributed processing of array streams. We have proposed the language ASTL, which is specifically intended for stream processing in a Grid environment, and completed a program of research into type theory to support distributed inference of stream properties. An ASTL implementation is well underway, with a PhD project focusing on it and a collaborative research programme with a German university being funded by EPSRC.

Some of the current challenges are:

• Expansion of the ASTL type system towards user-defined homomorphically overloaded operators.
• Shape inference, or at least shape characterisation, of arrays using either the formalism developed by the German collaborators, or our original one, with a subsequent evaluation.
• Distributed implementation of ASTL using Globus and GridMPI

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Computer Architecture Research

Research is targeted around the Hatfield Superscalar Architecture (HSA). The HSA is concerned with the exploitation of instruction-level parallelism in multiple-instruction issue processors. Our research involves:

• Developing and implementing algorithms to extract instruction-level parallelism at compile time.
• Designing superscalar processors to extract instruction-level parallelism at run time.

Numerous empirical studies suggest that many of the instructions executed in a sequential program can theoretically be executed in parallel without altering the program semantics. To exploit this potential parallelism, instructions which are initially widely separated within a program have to be grouped together for parallel execution at run time. We use an additional compiler pass to perform this instruction scheduling.

Some of the current challenges are:

• Investigating the upper-limits of instruction parallelism.
• Dynamic Branch Prediction
• Multithreading
• Instruction Scheduling.
• Developing novel architectural models.

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Grants

We have been awarded the following grants to support our research:

• A Multithreaded Approach to the Problem of Difficult to Predict Branches
  • EPSRC Grant GR/S58492/01
• Cached Dynamic Branch Prediction
  • Royal Society Grant 574006.G503/23904/SM
• Type and Shape Inference in Single Assignment languages for Array Processing
  • EPSRC Grant GR/S26484/01

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Some Recent CTCA Publications

• A. Shafarenko. Coercion as homomorphism: type inference in a system with subtyping and overloading"Fourth ACM SIGPLAN Conference on Principles and Practivce of Declarative Programming PPDP'02
• Egan, C., Steven, G. B., and Vintan, L.A Cached Two-level Adaptive Branch Predictors with Multiple Stages In Trends in Network and Pervasive Computing - ARCS 2002 (Lecture Notes in Computer Science 2299), Springer-Verlag, pp. 179 - 191, 2002.
• A.Shafarenko. Symmetry-based formalism for array subtyping. APL Quote Quad March, 2001, pp41-52 48.
• A Shafarenko and V Vasekin. An adaptive, reconfigurable interconnect for computational clusters. Proceedings First IEEE/ACM International Symposium on Cluster Computing and the Grid. IEEE Comput. Soc, Los Alamitos, CA, USA; 2001; pp. 229-36.
• N. Antonopoulos, K. Koukoumpetsos and A. Shafarenko. Access control for agent-based computing: a distributed approach Internet Research, 2001, vol. 11, no. 1, pp. 55-64
• N.Antonopoulos, A.Shafarenko. An Active Organisation System for Customised, Secure Agent Discovery. The Journal of Supercomputing, 20 (1): 5-35, August 2001 47.
• Egan, C., Steven, G. B., Shim, W., and Vintan, L.A Applying Caching to Two-level Adaptive branch Prediction In Digital Systems Design Architectures, Methods and Tools. Warsaw, Poland. pp. 186 - 193, 2001.
• Steven, G.B., Anguera, R., Egan, C., Steven, F. and Vintan, L. Dynamic Branch Prediction Using Neural Networks In Digital Systems Design Architectures, Methods and Tools. Warsaw, Poland. pp 178 - 185, 2001.
• Steven, G. B., Egan, Shim, W., C., and Vintan, L.A A Cost-effective Two-level Adaptive Branch Predictor In 13th International Conference on Control Systems and Computer Science (CSCS-13), Sponsored by IEEE., Bucharest, Romania. pp. 438 - 445, 2001.
• Steven, G. B., Egan, C., and Vintan, L.A Cost Effective Cached Correlated Two-level Adaptive Branch Predictor. In IASTED 2000, Innsbruck, Austria. 2000.
• N. Antonopoulos, G. Aggelou and A. V. Shafarenko. Asynchronous Internet Computing Model and Its Applications. Conference on Practical Applications of Agents and Multi Agents Systems (PAAM99). London, UK, April 1999. pp 383-402
• N. Antonopoulos and A. V. Shafarenko. A Massively Aliasing System for Suppport of Agent-based Internet Computing. PDPTA99 Las Vegas, USA, July 1999. pp 869-875
• Vintan, L. and Egan, C., Extending Correlation in Branch Prediction Schemes In: Proceedings: Euromicro99 Conference, Sponsored by IEEE, Milan, pp 441 - 448, 1999.
• N. Antonopoulos, A. V. Shafarenko, G. Aggelou and R. Tafazolli. An Integrated Addressing and Routing System for Mobile Agents. PDPTA99 Las Vegas, USA, July 1999. pp. 2391-2397
• C.R.Jesshope and A.V.Shafarenko. Asynchrony in parallel computing: the question of scale MPCS-98 proceedings. Colorado Springs, USA, April 1998
• N. Antonopoulos and A. V. Shafarenko. An Asynchronous Computational Model for Internet Computing MPCS-98 proceedings. Colorado Springs, USA, April 1998.
• A.Bolychevsky, A.Shafarenko and V Vasekin. Reconfigurable Optical Interconnect in a scalable data-parallel system. DDP'98 Proceedings 38. Novosibirsk, 1998, pp. 59-64
• E.D. Willink, A.V.Shafarenko, V.B. Muchnick. Use of F-code as a Very High Level INtermediate Language for DSP In: Springer-Verlag Lecture Notes in Computer Science I1300, p. 820, 1997
• J A B Dines, J F Snowdon, M P Y Desmulliez, D T Nielson, D B Barsky, A V Shafarenko, C R Jesshope. Optical interconnectivity in a Scalable Data-Parallel System. Journal of Parallel and Distributed Computing, 41, 120-130 (1997)
• Steven, G. B., Egan, C., Quick, P. and Vintan, L., Reducing Cold Start Mispredictions in Two-level Adaptive Branch Predictors, In: 12th International Conference on Control Systems and Computer Science (CSCS-12), Sponsored by IEEE., Bucharest, pp 145 - 150, 1997.
• Egan, C., Steven, F. L. and Steven, G. B., Delayed Branches versus Dynamic Branch Prediction in a High-Performance Superscalar Architecture. In: Proceedings: Euromicro97 Conference, Sponsored by IEEE, Budapest, pp 266 - 271, 1997.
• R.D. Potter, F.L. Steven, G.B. Steven and L. Vintan. Static Data Dependence Collapsing in a High-Performance Superscalar Processor, The 3rd International Conference on Massively Parallel Computer Systems, Colorado, USA.
• G.B. Steven, B. Christian, R. Collins, R.D. Potter and F.L. Steven, A Superscalar Architecture To Exploit Instruction Level Parallelism, Microprocessors and Microsystems (Elvisier Science), 20, pp 391 - 400, 1997.
• A.Shafarenko. RETRAN: a recurrent paradigm for data-parallel computing. Computer Systems Science and Engineering, vol 11, No 4, July 1996, pp 201-209
• V B Muchnick and A V Shafarenko. Dynamic evaluation strategy for fine-grain data-parallel computing. IEE Proc.-Comput. Digit. Tech., v.143, No.3(1996), pp181-188.
• D B Barsky and A V Shafarenko. Uniform random traffic in a massively-parallel data-driven computer, MPCS' 96 Proceedings, IEEE Press, pp 546-553.
• J A B Dines, J F Snowdon, M P Y Desmulliez, D T Nielson, D B Barsky, A V Shafarenko, C R Jesshope. Optical interconnection hardware for scalable systems. Proc. of International Conference on Parallel and Distributed Processing Techniques and Applications, H.R.Arabnia (Editor), published by CSREA, Aug 9-11,1996, Sunnyvale USA, pp367-374.
• C.J. Elston, B. Christianson, P.A. Findlay and G.B. Steven. HADES: An Asynchronous Superscalar Processor, Proc. of IEE Colloquium on the Design and Test of Asynchronous Systems, London, pp10/1-10/6, February 1996.
• R.D. Potter, Investigating the Limits of Instruction Level Parallelism, Division of Computer Science Technical Report. 1996
• R.D. Potter and G.B. Steven. Investigating the Limits of Fine-Grained Parallelism in a Statically Scheduled Superscalar Architecture, 2nd Int. Euro-par, Vol. 2, pp 779-788, August 1996. (Published as LLNCS by Springer Verlag).
• G.B. Steven and R. Collins. Instruction Scheduling for a Supersclar Architecture, Proc. of the 22nd Euromicro Conf., Prague, pp 643-650, September 1996.
• G.B. Steven and L. Vintan. Modelling Superscalar Pipelines with Finite State Machines, Proc of Euromicro96, Prague, September 1996.

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Other Resources

• CAPSL Homepage
• Faculty of Engineering and Information Sciences
• Foldoc electronic dictionary of computing
• Simplescalar Simulator Homepage
• WWW Computer Architecture Home Pages

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Last Updated: 25/11/2004 by Colin Egan

© University of Hertfordshire Higher Education Corporation (2004)

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